1. Field of the Invention
The present invention relates to a timing controller and a delay circuit (controlled delay circuit), and more particularly, to a timing controller adopted for electronic circuits, for controlling the timing of a signal by changing the phase of the signal.
2. Description of the Related Art
Recent computers employ high-speed CPUs (central processing units: MPUS) and electronic circuits. These high-speed devices require high-speed interfaces.
The access time of a synchronous memory (for example, synchronous dynamic random access memory: SDRAM) is basically determined by a delay time in an input buffer, a delay time in long wiring, and a delay time in an output buffer. These delay times are reducible only by reducing the chip size or by improving the transistor characteristics. It is very difficult, therefore, to provide high-speed synchronous memories.
LSI chips are becoming larger, and the delay time in the long wiring reaches one nanosecond or more. These are many LSIs that have an access time of five nanoseconds or longer. The long access time limits the rate of continuous access operations to about 100 MHz.
On the other hand, the signal frequency inside a chip can be increased by employing a pipeline structure and parallel-serial conversion. An output circuit of the chip, however, is incapable of following the internal speed of the chip. It is required, therefore, to provide a timing controller for properly controlling the timing of a control signal to the output circuit according to the period of the control signal. The problems of the prior art will be explained hereinafter in detail with reference to the accompanying drawings.